Altera cyclone V Technical Reference page 632

Hard processor system
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8-50
Slave Register Group Register Descriptions
31
30
15
14
fn_mod Fields
Bit
1
wr
0
rd
Slave Register Group Register Descriptions
Registers associated with slave interfaces.
Offset:
0x42000
L3 Slave Register Group Register Descriptions
Registers associated with the 32-bit AXI slave interface. This slave connects to the L3 Interconnect.
Offset:
0x3000
fn_mod
on page 8-50
Sets the block issuing capability to multiple or single outstanding transactions.
fn_mod
Sets the block issuing capability to multiple or single outstanding transactions.
Module Instance
lwhps2fpgaregs
Offset:
0x45108
Access:
RW
Altera Corporation
29
28
27
26
13
12
11
10
Name
Value
0x0
0x1
Value
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Reserved
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
Description
Multiple outstanding read transactions
Only a single outstanding read transaction
Base Address
0xFF400000
21
20
19
18
5
4
3
2
Access
Register Address
0xFF445108
cv_5v4
2016.10.28
17
16
1
0
wr
rd
RW
RW 0x0
0x0
Reset
RW
0x0
RW
0x0
HPS-FPGA Bridges
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