Functional Description Of The Hps-Fpga Bridges - Altera cyclone V Technical Reference

8-4

Functional Description of the HPS-FPGA Bridges

Functional Description of the HPS-FPGA Bridges
The Global Programmers View
The HPS-to-FPGA bridge includes a set of registers called the GPV. The GPV provides settings to control
the bridge properties and behavior. Access to the GPV registers of all three bridges is provided through the
lightweight HPS-to-FPGA bridge.
The GPV registers can only be accessed by secure masters in the HPS or the FPGA fabric.
Functional Description of the FPGA-to-HPS Bridge
The FPGA-to-HPS bridge provides access to the peripherals and memory in the HPS. This access is
available to any master implemented in the FPGA fabric. You can configure the bridge slave, which is
exposed to the FPGA fabric, to support 32-, 64-, or 128-bit data. The master interface of the bridge,
connected to the L3 interconnect, has a data width of 64 bits.
Table 8-2: FPGA-to-HPS Bridge Properties
The following table lists the properties of the FPGA-to-HPS bridge, including the configurable slave
interface exposed to the FPGA fabric.
Bridge Property
Data width
(19)
Clock domain
Byte address width
ID width
Read acceptance
Write acceptance
Total acceptance
The FPGA-to-HPS bridge address map contains a GPV. The GPV registers provide settings that adjust the
bridge slave properties when the FPGA slave interface is configured to be 32 or 128 bits wide. The slave
issuing capability can be adjusted, through the
outstanding in the HPS. The slave bypass merge feature can also be enabled, through the
bit in the
fn_mod2
transactions when the FPGA slave interface is configured to be 32 or 128 bits wide.
Note: It is critical to provide the correct
"GPV Clocks".
The bridge slave data width is user-configurable at the time you instantiate the HPS component in your
(19)
system.
Altera Corporation
FPGA Slave Interface
32, 64, or 128 bits
f2h_axi_clk
32 bits
8 bits
16 transactions
16 transactions
32 transactions
register. This feature ensures that the upsizing and downsizing logic does not alter any
l4_mp_clk
64 bits
l3_main_clk
32 bits
8 bits
16 transactions
16 transactions
32 transactions
register, to allow one or multiple transactions to be
fn_mod
clock to support access to the GPV, as described in
2016.10.28
L3 Master Interface
bypass_merge
HPS-FPGA Bridges
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