Fpga Manager Block Diagram And System Integration - Altera cyclone V Technical Reference

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FPGA Manager Block Diagram and System Integration

Figure 4-1: FPGA Manager Block Diagram

Interconnect

The register slave interface connects to the level 4 (L4) master peripheral bus for control and status register

(CSR) access. The configuration slave interface connects to the level 3 (L3) interconnect for the microproc‐

essor unit (MPU) subsystem or other masters to write the FPGA configuration image to the FPGA control

block (CB) when configuring the FPGA portion of the SoC device.

The general-purpose I/O and boot handshake input interfaces connect to the FPGA fabric. The FPGA

manager also connects to the FPGA CB signals to monitor and control the FPGA portion of the device.

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FPGA Manager

Configuration

CONFIG_IO Mode

CVP_CONF_DONE

h2f_gp[31:0]

f2h_gp[31:0]

f2h_boot_from_fpga_on_failure

f2h_boot_from_fpga_ready

FPGA Portion

Control Block

FPGA Manager

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