Hardware-Managed And Software-Managed Clocks; Clock Groups - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Clock Gating
Clock gating enables and disables clock signals. Refer to the Peripheral PLL Group Enable Register (
more information on what clocks can be gated.
Related Information
Clock Manager Address Map and Register Definitions
Control and Status Registers
The Clock Manager contains registers used to configure and observe the clock manager.

Hardware-Managed and Software-Managed Clocks

When changing values on clocks, the terms hardware-managed and software-managed define who is
responsible for successful transitions. Software-managed clocks require that software manually gate any
clock affected by the change, wait for any PLL lock if required, then ungate the clocks. Hardware-managed
clocks use hardware to ensure that a glitch-free transition to a new clock value occurs. There are three
hardware-managed sets of clocks in the HPS, namely, clocks generated from the main PLL outputs C0, C1,
and C2. All other clocks in the HPS are software-managed clocks.

Clock Groups

The clock manager contains one clock group for each PLL and one clock group for the
and
HPS_CLK1
For more information on
Related Information
Cyclone V Device Datasheet
OSC1 Clock Group
The clock in the OSC1 clock group is derived directly from the
divided.
is used as a PLL input and also by HPS logic that does not operate on a clock output from a PLL.
HPS_clk1
Table 2-4: OSC1 Clock Group Clock
Name
osc1_clk
Main Clock Group
The main clock group consists of a PLL, dividers, and clock gating. The clocks in the main clock group are
derived from the main PLL. The main PLL is always sourced from the
Clock Manager
Send Feedback
are powered by the HPS reset and clock input pins power supply (
HPS_CLK2
V _HPS
CCRSTCLK
Frequency
0 to 100 MHz
on page 2-23
refer to the Cyclone V Device Datasheet.
HPS_CLK1
Clock Source
pin
HPS_CLK1
Clock Gating
HPS_CLK1
V
CCRSTCLK
pin. This clock is never gated or
Destination
OSC1-driven
peripherals. Refer to
"Main Clock Group
Clocks".
pin of the device.
HPS_CLK1
Altera Corporation
2-7
) for
en
pin.
).
_HPS