Single-Port Controller - Altera cyclone V Technical Reference

11-8

Single-Port Controller

Write Data Block
The write data block transmits data to the single-port controller. The write data block maintains write data
FIFO buffers and clock boundary crossing for the write data. The write data block informs the command
block of the amount of pending write data for each transaction so that the command block can calculate
eligibility for the next SDRAM write burst.
Read Data Block
The read data block receives data from the single-port controller. Depending on the port state, the read
data block either buffers the data in its internal buffer or passes the data straight to the clock boundary
crossing FIFO buffer. The read data block reorders out-of-order data for Avalon-MM ports.
In order to prevent the read FIFO buffer from overflowing, the read data block informs the command
block of the available buffer area so the command block can pace read transaction dispatch.
Single-Port Controller
The single-port logic is responsible for following actions:
• Queuing the pending SDRAM bursts
• Choosing the most efficient burst to send next
• Keeping the SDRAM pipeline full
• Ensuring all SDRAM timing parameters are met
Transactions passed to the single-port logic for a single page in SDRAM are guaranteed to be executed in
order, but transactions can be reordered between pages. Each SDRAM burst read or write is converted to
the appropriate Altera PHY interface (AFI) command to open a bank on the correct row for the transac‐
tion (if required), execute the read or write command, and precharge the bank (if required).
The single-port logic implements command reordering (looking ahead at the command sequence to see
which banks can be put into the correct state to allow a read or write command to be executed) and data
reordering (allowing data transactions to be dispatched even if the data transactions are executed in an
order different than they were received from the multi-port logic).
The single-port controller consists of eight sub-modules.
Command Generator
The command generator accepts commands from the MPFE and from the internal ECC logic, and
provides those commands to the timer bank pool.
Related Information
Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.
Timer Bank Pool
The timer bank pool is a parallel queue that operates with the arbiter to enable data reordering. The timer
bank pool tracks incoming requests, ensures that all timing requirements are met, and, on receiving write-
data-ready notifications from the write data buffer, passes the requests to the arbiter
Related Information
Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.
Altera Corporation
on page 11-6
on page 11-6
cv_5v4
2016.10.28
SDRAM Controller Subsystem
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