Operating States - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Access Type
DMA Privileged.
manager Secure state
instruction from DNS
fetch bit.
DMA Privileged.
channel Secure state
instruction from
fetch CNS
Note: Cacheable accesses must be mapped to
contains the only addresses that the DMA can use to access the following:
• Instructions — Always cacheable
• Data — Caching dictated by the DMA channelmicrocode
ARLEN and ARSIZE for Instruction Fetches
When performing an instruction fetch, the DMAC sets
• Instruction cache length ≤ AXI data bus width
•
ARLEN
•
ARSIZE
• Instruction cache length > AXI data bus width
•
ARLEN
bytes
•
ARSIZE

Operating States

The following figure shows the transitions among operating states for the DMA manager thread and DMA
channel threads. The DMAC provides a separate state machine for each thread.
(54) The DSR Register contains the DNS bit. For more information, refer to the "DMA Manager Status Register"
chapter in the CoreLink DMA Controller DMA-330 Revision: r1p2 Technical Reference Manual.
The CSR Register contains the CNS bit for DMA channel <n>. For more information, refer to the
(55)
n
"Channel Status Registers" chapter in the CoreLink DMA Controller DMA-330 Revision: r1p2 Technical
Reference Manual.
DMA Controller
Send Feedback
Protection Length
(54)
See
ARLEN
for
ARSIZE
instruction
fetches.
bit.
(55)
= 1
= length of instruction cache in bytes
= ratio of the length of an instruction cache line in bytes to the width of the AXI data bus in
= width of AXI data bus in bytes
Burst
and
See
ARSIZE
INCR
instruction
fetches.
0x80000000 — 0xBFFFFFFF
and
ARLEN
Operating States
Size Cache
and • Cacheable write-
ARLEN
for through
• Allocate on reads
only
. The ACP Window range
as follows:
ARSIZE
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