Altera cyclone V Technical Reference page 322

5-128
GENERALIO2
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GENERALIO1 Fields
Bit
1:0
sel
GENERALIO2
This register is used to control the peripherals connected to trace_d1 Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x488
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected trace_d0. 0 : Pin is
connected to GPIO/LoanIO number 49. 1 : Pin is
connected to Peripheral signal UART0.RX. 2 : Pin is
connected to Peripheral signal SPIS0.CLK. 3 : Pin is
connected to Peripheral signal TRACE.D0.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD08488
21 20 19 18
5 4 3 2
cv_5v4
2016.10.28
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
System Manager
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