Altera cyclone V Technical Reference page 211
Hard processor system
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Also See for cyclone V:
- Device handbook (1077 pages) ,
- User manual (136 pages) ,
- Reference manual (66 pages)
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cv_5v4
2016.10.28
Register
MIXED1IO8
on page 5-
141
MIXED1IO9
on page 5-
142
MIXED1IO10
on page 5-
142
MIXED1IO11
on page 5-
143
MIXED1IO12
on page 5-
144
MIXED1IO13
on page 5-
145
MIXED1IO14
on page 5-
145
MIXED1IO15
on page 5-
146
MIXED1IO16
on page 5-
147
MIXED1IO17
on page 5-
148
MIXED1IO18
on page 5-
148
MIXED1IO19
on page 5-
149
MIXED1IO20
on page 5-
150
MIXED1IO21
on page 5-
151
MIXED2IO0
on page 5-
151
MIXED2IO1
on page 5-
152
MIXED2IO2
on page 5-
153
MIXED2IO3
on page 5-
154
MIXED2IO4
on page 5-
154
MIXED2IO5
on page 5-
155
System Manager
Send Feedback
Offset
Width Acces
s
0x520
32
RW
0x524
32
RW
0x528
32
RW
0x52C
32
RW
0x530
32
RW
0x534
32
RW
0x538
32
RW
0x53C
32
RW
0x540
32
RW
0x544
32
RW
0x548
32
RW
0x54C
32
RW
0x550
32
RW
0x554
32
RW
0x558
32
RW
0x55C
32
RW
0x560
32
RW
0x564
32
RW
0x568
32
RW
0x56C
32
RW
System Manager Module Address Map
Reset Value
nand_dq3 Mux Selection Register
0x0
nand_dq4 Mux Selection Register
0x0
nand_dq5 Mux Selection Register
0x0
nand_dq6 Mux Selection Register
0x0
nand_dq7 Mux Selection Register
0x0
nand_wp Mux Selection Register
0x0
nand_we Mux Selection Register
0x0
qspi_io0 Mux Selection Register
0x0
qspi_io1 Mux Selection Register
0x0
qspi_io2 Mux Selection Register
0x0
qspi_io3 Mux Selection Register
0x0
qspi_ss0 Mux Selection Register
0x0
qpsi_clk Mux Selection Register
0x0
qspi_ss1 Mux Selection Register
0x0
emac1_mdio Mux Selection
0x0
Register
emac1_mdc Mux Selection
0x0
Register
emac1_tx_d2 Mux Selection
0x0
Register
emac1_tx_d3 Mux Selection
0x0
Register
emac1_rx_clk Mux Selection
0x0
Register
emac1_rx_ctl Mux Selection
0x0
Register
5-17
Description
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