Altera cyclone V Technical Reference page 610

8-28
Master Register Group Register Descriptions
comp_id_3 Fields
Bit
7:0
preamble
Master Register Group Register Descriptions
Registers associated with master interfaces.
Offset:
0x2000
32-bit Master Register Descriptions
Registers associated with the 32-bit AXI master interface. These registers are only active when the
HPS2FPGA AXI Bridge is configured with a 32-bit FPGA AXI master interface.
Offset:
0x0
fn_mod2
Controls bypass merge of upsizing/downsizing.
fn_mod on page 8-29
Sets the block issuing capability to multiple or single outstanding transactions.
fn_mod2
Controls bypass merge of upsizing/downsizing.
Module Instance
hps2fpgaregs
Offset:
0x2024
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
Preamble
on page 8-28
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Base Address
0xFF500000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Access
Register Address
0xFF502024
21 20 19 18
5 4 3 2
cv_5v4
2016.10.28
Reset
RO 0xB1
17 16
1 0
bypass_
merge
RW 0x0
HPS-FPGA Bridges
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