Altera cyclone V Technical Reference page 436

6-4
ARM JTAG-AP Scan Chains
can send JTAG commands (such as the
responses to determine details about CRC errors detected by the control block when the FPGA fabric is in
user mode. Through the FPGA manager, software can determine that a CRC error was detected. For more
information about the TAP controller, refer to the Communicating with the JTAG TAP Controller section of
this chapter.
Scan chains 0 to 3 of the JTAG-AP connect to the configuration information in the HPS I/O scan chain
banks through the I/O configuration shift register (IOCSR) multiplexer. For more information, refer to the
Configuring HPS I/O Scan Chains section of this chapter.
Note: The I/O scan chains do not use the JTAG protocol. The scan manager uses the JTAG-AP as a
parallel-to-serial converter for the I/O scan chains. The I/O scan chains are connected only to the
serial output data (
The HPS I/O pins are divided into six banks. Each I/O bank is either a vertical (VIO) or horizontal (HIO)
I/O, based on its location on the die.
Table 6-1: Bank Usage of IOCSR Scan Chains
The following table shows the mapping of the IOCSR scan chains to the I/O banks.
IOCSR Scan Chain
0
1
2
3
When the FPGA JTAG TAP controller is in
manager JTAG-AP and configure the HPS I/O pins. For more information, refer to the Configuring HPS
I/O Scan Chains section of this chapter.
Note:
CONFIG_IO
boundary scan testing.
Note: The HPS JTAG pins and the following HPS I/O pins do not support boundary scan tests (BST):
• DDR SDRAM
• OSC1/2
• Warm/Cold reset
To perform boundary scan testing on HPS I/O pins, use the FPGA JTAG.
Related Information
Configuring HPS I/O Scan Chains
•
Altera Corporation
SHIFT_EDERROR_REG
JTAG signal) and serial clock (
TDI
Bank Type
VIO
VIO
VIO
HIO
mode is commonly used to configure the I/O pin properties prior to performing
on page 6-5
JTAG instruction) to the FPGA JTAG and get
JTAG signal).
TCK
HPS I/O Bank
I/O bank 7D and I/O bank
7E
I/O bank 7B and I/O bank
7C
I/O bank 7A
I/O bank 6
mode, the controller can override the scan
CONFIG_IO
2016.10.28
Usage
EMAC
SD/MMC, NAND, and
quad SPI
2
Trace, SPI, UART, I C,
and CAN
SDRAM DDR
Scan Manager
Send Feedback
cv_5v4