Altera cyclone V Technical Reference page 272

5-78
emac0
Offset:
0x14C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
usb1 Fields
Bit
4
derr
3
serr
2
injd
1
injs
0
en
emac0
This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
This bit is an interrupt status bit for USB1 RAM ECC
double bit, non-correctable error. It is set by hardware
when double bit, non-correctable error occurs in
USB1 RAM. Software needs to write 1 into this bit to
clear the interrupt status.
This bit is an interrupt status bit for USB1 RAM ECC
single, correctable error. It is set by hardware when
single, correctable error occurs in USB1 RAM.
Software needs to write 1 into this bit to clear the
interrupt status.
Changing this bit from zero to one injects a double,
non-correctable error into the USB1 RAM. This only
injects one double bit error into the USB1 RAM.
Changing this bit from zero to one injects a single,
correctable error into the USB1 RAM. This only
injects one error into the USB1 RAM.
Enable ECC for USB1 RAM
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
21 20 19 18
5 4 3 2
derr serr injd
RW RW RW
0x0 0x0 0x0
Access
cv_5v4
2016.10.28
17 16
1 0
injs en
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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