Altera cyclone V Technical Reference page 429

cv_5v4
2016.10.28
I2C2USEFPGA
Selection between HPS Pins and FPGA Interface for I2C2 signals. Only reset by a cold reset (ignores warm
reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x728
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
I2C2USEFPGA Fields
Bit
0
sel
I2C1USEFPGA
Selection between HPS Pins and FPGA Interface for I2C1 signals. Only reset by a cold reset (ignores warm
reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x72C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Manager
Send Feedback
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select connection for I2C2. 0 : I2C2 uses HPS Pins. 1 :
I2C2 uses the FPGA Inteface.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
I2C2USEFPGA
Register Address
0xFFD08728
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD0872C
5-235
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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