Data Width Sizing - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
GPV Clocks
The FPGA-to-HPS and HPS-to-FPGA bridges have GPV slave interfaces, mastered by the lightweight
HPS-to-FPGA bridge. These interfaces operate in the
lightweight HPS-to-FPGA bridge in your FPGA design, you must ensure that a valid
being generated, so that the GPV registers in the HPS-to-FPGA and FPGA-to-HPS bridges can be
programmed. The GPV logic in all three bridges is in the
Related Information
The Global Programmers View

Data Width Sizing

The HPS-to-FPGA and FPGA-to-HPS bridges allow 32-, 64-, and 128-bit interfaces to be exposed to the
FPGA fabric. For 32-bit and 128-bit interfaces, the bridge performs data width conversion to the fixed 64-
bit interface within the HPS. This conversion is called upsizing in the case of data being converted from a
64-bit interface to a 128-bit interface. It is called downsizing in the case of data being converted from a 64-
bit interface to a 32-bit interface. If an exclusive access is split into multiple transactions, the transactions
lose their exclusive access information.
During the upsizing or downsizing process, transactions can also be resized using a data merging
technique. For example, in the case of a 32-bit to 64-bit upsizing, if the size of each beat entering the
bridge's 32-bit interface is only two bytes, the bridge can merge up to four beats to form a single 64-bit
beat. Similarly, in the case of a 128-bit to 64-bit downsizing, if the size of each beat entering the bridge's
128-bit interface is only four bytes, the bridge can merge two beats to form a single 64-bit beat.
The bridges do not perform transaction merging for accesses marked as noncacheable.
Note: You can set the
responses. If the bridge merges multiple responses into a single response, that response is the one
with the highest priority. The response types have the following priorities:
1. DECERR
2. SLVERR
3. OKAY
HPS-FPGA Bridges Address Map and Register Definitions
The address map and register definitions for the HPS-FPGA bridges consist of the following regions:
• FPGA-to-HPS Bridge Module
• HPS-to-FPGA Bridge Module
• Lightweight HPS-to-FPGA Bridge Module
• FPGA Slaves Accessed via Lightweight HPS-to-FPGA AXI Bridge
Related Information
• FPGA2HPS AXI Bridge Module Address Map
HPS2FPGA AXI Bridge Module Address Map
•
LWHPS2FPGA AXI Bridge Module Address Map
•
HPS-FPGA Bridges
Send Feedback
on page 8-4
bit in the GPV to prevent the bridge from merging data and
bypass_merge
clock domain. Even if you do not use the
l4_mp_clk
domain.
l4_mp_clk
on page 8-7
on page 8-20
on page 8-35
8-53
GPV Clocks
clock is
l4_mp_clk
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