Address Map And Register Definitions - Altera cyclone V Technical Reference

16-62

Address Map and Register Definitions

• Control registers— allow you to control the DMAC.
• DMA channel thread status registers—provide the status of the DMA channel threads.
• AXI and loop counter status registers—provide the AXI transfer status and the loop counter status for
each DMA channel thread.
• Debug registers—enable the following functionality:
• Allow you to send instructions to a thread when debugging the program code.
• Allow system firmware to send instructions to the DMA manager thread.
• Configuration registers—enable system firmware to identify the configuration of the DMAC and
control the behavior of the watchdog.
• Component ID registers— enable system firmware to identify peripherals. Do not attempt to access
reserved or unused address locations. Attempting to access these locations can result in an unpredict‐
able behavior.
Address Map and Register Definitions
The address map and register definitions for the DMA Controller consist of the following regions:
• Nonsecure DMA Module Address Space
• Secure DMA Module Address Space
Secure DMA Module Address Map
This address space is allocated for secure DMA accesses. For detailed information about the use of this
address space,
Related Information
Introduction to the Hard Processor System
The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter.
Secure DMA Module Address Map
This address space is allocated for secure DMA accesses. For detailed information about the use of this
address space,
Table 16-7: Secure DMA Module Address Range
Module Instance
secure_dma
Table 16-8: Secure DMA Register Space
Register Group
Control
Reserved
Altera Corporation
on page 16-62
click here to access the ARM documentation for the DMA-330.
click here
to access the ARM documentation for the DMA-330.
0xFFE01000
Description
This address space is
allocated for DMA
control registers.
This address space is
reserved.
on page 1-1
Start Address
Start Address
0xFFE01000
0xFFE01060
End Address
0xFFE01FFF
End Address
0xFFE0105F
0xFFE010FF
DMA Controller
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cv_5v4
2016.10.28