Altera cyclone V Technical Reference page 95

2-58
div
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
div Fields
Bit
11:9
can1clk
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
can1clk
RW 0x0
Name
The can1_clk is divided down from the periph_base_
clk by the value specified in this field.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Bit Fields
25 24 23 22
Reserved
9 8 7 6
can0clk
RW 0x0
Description
Value Description
Divide By 1
Divide By 2
Divide By 4
Divide By 8
Divide By 16
Reserved
Reserved
Reserved
21 20 19 18
5 4 3 2
spimclk
RW 0x0
Access
cv_5v4
2016.10.28
17 16
1 0
usbclk
RW 0x0
Reset
RW 0x0
Clock Manager
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