Reset Handshaking; Reset Manager Address Map And Register Definitions - Altera cyclone V Technical Reference

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Reset Handshaking

The following suggestions provide ways to alter the system response to a warm reset. None of the register
bits that control these items are affected by warm reset.
• Boot from on-chip RAM—enables warm boot from on-chip RAM instead of the boot ROM. When
enabled, the boot ROM code validates the RAM code and jumps to it, making no changes to clocks or
any other system settings prior to executing user code from on-chip RAM.
• Disable safe mode on warm reset—allows software to transition through a warm reset without affecting
the clocks. Because the boot ROM code indirectly configures the clock settings after warm reset, Altera
recommends that safe mode should only be disabled when the HPS is not booting from a flash device.
• Disable safe mode on warm reset for the debug clocks—keeps the debug clocks from being affected by
the assertion of safe mode request on a warm reset. This technique allows fast debug clocks, such as
trace, to continue running through a warm reset. When enabled, the clock manager configures the
debug clocks to their safe frequencies to respond to a safe mode request from the reset manager on a
warm reset. Disable safe mode on warm reset for the debug clocks only when you are running the
debug clocks off the main PLL VCO and you are certain the main PLL cannot be impacted by the event
which caused the warm reset.
• Use the
bypassed to the
implemented, disabling safe mode on warm reset for the debug clocks has no effect.
Related Information
Clock Manager
For more information about safe mode, refer to the Clock Manager chapter.
Reset Handshaking
The reset manager participates in several reset handshaking protocols to ensure other modules are safely
reset.
Before issuing a warm reset, the reset manager performs a handshake with several modules to allow them
to prepare for a warm reset. The handshake logic ensures the following conditions:
• Optionally the ETR master has no pending master transactions to the L3 interconnect
• Optionally preserve SDRAM contents during warm reset by issuing self-refresh mode request
• FPGA manager stops generating configuration clock
• Scan manager stops generating JTAG and I/O configuration clocks
• Warns the FPGA fabric of the forthcoming warm reset
Similarly, the handshake logic associated with ETR also occurs during the debug reset to ensure that the
ETR master has no pending master transactions to the L3 interconnect before the debug reset is issued.
This action ensures that when ETR undergoes a debug reset, the reset has no adverse effects on the system
domain portion of the ETR.

Reset Manager Address Map and Register Definitions

The address map and register definitions for the HPS-FPGA bridge consist of the following regions:
• Reset Manager Module
Altera Corporation
clock for debug control—keeps the debug base clock (main PLL C2 output) always
osc1_clk
external clock, independent of other clock manager settings. When
osc1_clk
on page 2-1
cv_5v4
2016.10.28
Reset Manager
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