Altera cyclone V Technical Reference page 483

cv_5v4
2016.10.28
l4spim
on page 7-45
Controls security settings for L4 SPIM peripherals.
stm on page 7-47
Controls security settings for STM peripheral.
lwhps2fpgaregs
Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral.
usb1 on page 7-49
Controls security settings for USB1 Registers peripheral.
nanddata
on page 7-50
Controls security settings for NAND Flash Controller Data peripheral.
usb0 on page 7-51
Controls security settings for USB0 Registers peripheral.
nandregs
on page 7-52
Controls security settings for NAND Flash Controller Registers peripheral.
qspidata on page 7-53
Controls security settings for QSPI Flash Controller Data peripheral.
fpgamgrdata
Controls security settings for FPGA Manager Data peripheral.
hps2fpgaregs
Controls security settings for HPS2FPGA AXI Bridge Registers peripheral.
acp
on page 7-56
Controls security settings for MPU ACP peripheral.
rom on page 7-57
Controls security settings for ROM peripheral.
ocram
on page 7-58
Controls security settings for On-chip RAM peripheral.
sdrdata on page 7-59
Controls security settings for SDRAM Data peripheral.
l4main
Controls security settings for L4 main peripherals
Module Instance
l3regs
Offset:
0x8
Access:
WO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Interconnect
Send Feedback
on page 7-48
on page 7-54
on page 7-55
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
0xFF800008
7-35
l4main
Register Address
Altera Corporation