Aborts - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Interrupting the MPU Subsystem
The DMAC provides the
subsystem. When you program the
, it sets the corresponding
DMASEV
The MPU subsystem can clear the interrupt by writing to the
Note: Executing
If you use the
instruction then you should insert a memory barrier instruction before the
might signal an interrupt before the AXI transfers complete.
The following program shows the example of Memory Barrier Instruction.
DMALD
DMAST
# Issue a write memory barrier
# Wait for the AXI write transfer to complete before the DMAC
# can send an interrupt
DMAWMB
# The DMAC sends the interrupt
DMASEV

Aborts

Abort Types
An abort can be classified as either precise or imprecise, depending on whether the DMAC provides an
abort handler with the precise state of the DMAC when the abort occurs.
• Precise Abort - The DMAC updates the
abort.
• Imprecise Abort - The
abort to occur.
Abort Sources
The DMAC indicates a precise abort under any of the following conditions:
• A DMA channel thread in the Non-secure state attempts to program its
secure AXI transaction.
• A DMA channel thread in the Non-secure state executes
secure. The
Note: For each event, the
DMA Controller
Send Feedback
signals for use as active-high level-sensitive interrupts to the MPU
irq[x]
INTEN
irq[x]
does not clear an interrupt.
DMAWFE
instruction to notify a microprocessor when the DMAC completes a
DMASEV
register might contain the address of an instruction that did not cause the
PC
memory-mapped control signals initialize the security state for an event.
boot_irq_ns
register controls if the DMAC generates an event or signals an interrupt.
INTEN
Interrupting the MPU Subsystem
register to generate an interrupt, after the DMAC executes
signal high.
INTCLR
register with the address of the instruction that created the
PC
DMAWFE
register.
DMALD
. Otherwise the DMAC
DMASEV
register and generate a
CCRn
or for an event that is set as
DMASEV
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or
DMAST