Altera Cyclone V Manuals

Manuals and User Guides for Altera Cyclone V. We have 5 Altera Cyclone V manuals available for free PDF download: Technical Reference, Device Handbook, User Manual, Reference Manual, Boot Manual

Altera Cyclone V Technical Reference (3536 pages)

Hard Processor System

Brand: Altera | Category: Computer Hardware | Size: 24.75 MB

Table of Contents
2
Introduction to the Hard Processor System

17
- Features of the HPS
  19
- HPS Block Diagram and System Integration
  20
  - HPS Block Diagram
    20
  - Cortex-A9 Mpcore
    21
  - HPS Interfaces
    21
  - System Interconnect
    22
  - On-Chip Memory
    23
  - Flash Memory Controllers
    24
  - Support Peripherals
    25
  - Interface Peripherals
    27
  - Coresight Debug and Trace
    30
- Endian Support
  31
- Introduction to the Hard Processor System Address Map
  31
  - HPS Address Spaces
    31
  - HPS Peripheral Region Address Map
    33
- Document Revision History
  36
Clock Manager

38
- Features of the Clock Manager
  38
- Clock Manager Block Diagram and System Integration
  39
  - L4 Peripheral Clocks
    40
- Functional Description of the Clock Manager
  41
  - Clock Manager Building Blocks
    41
  - Hardware-Managed and Software-Managed Clocks
    44
  - Clock Groups
    44
  - Resets
    54
  - Safe Mode
    54
  - Interrupts
    55
  - Clock Usage by Module
    55
- Clock Manager Address Map and Register Definitions
  60
  - Clock Manager Module Address Map
    61
- Document Revision History
  110
Reset Manager

112
- Reset Manager Block Diagram and System Integration
  113
  - HPS External Reset Sources
    114
  - Reset Controller
    115
  - Module Reset Signals
    116
  - Slave Interface and Status Register
    121
- Functional Description of the Reset Manager
  121
  - Reset Sequencing
    122
  - Reset Pins
    126
  - Reset Effects
    126
  - Altering Warm Reset System Response
    126
  - Reset Handshaking
    127
- Reset Manager Address Map and Register Definitions
  127
  - Reset Manager Module Address Map
    128
- Document Revision History
  143
FPGA Manager

144
- Features of the FPGA Manager
  144
- FPGA Manager Block Diagram and System Integration
  145
- Functional Description of the FPGA Manager
  146
  - FPGA Manager Building Blocks
    146
  - FPGA Configuration
    147
  - FPGA Status
    151
  - Error Message Extraction
    151
  - Boot Handshake
    151
  - General Purpose I/O
    152
  - Clock
    152
  - Reset
    152
- FPGA Manager Address Map and Register Definitions
  152
  - FPGA Manager Module Configuration Data Address Map
    152
  - FPGA Manager Module Address Map
    153
- Document Revision History
  194
System Manager

195
- Features of the System Manager
  195
- System Manager Block Diagram and System Integration
  196
- Functional Description of the System Manager
  197
  - Boot Configuration and System Information
    197
  - Additional Module Control
    197
  - Dma Controller
    198
  - Boot ROM Code
    200
  - FPGA Interface Enables
    202
  - ECC and Parity Control
    202
  - Preloader Handoff Information
    203
  - Clocks
    203
  - Resets
    203
- System Manager Address Map and Register Definitions
  203
- Document Revision History
  431
Scan Manager

433
- Features of the Scan Manager
  433
- Scan Manager Block Diagram and System Integration
  434
  - ARM JTAG-AP Scan Chains
    435
- Functional Description of the Scan Manager
  437
  - Communicating with the JTAG TAP Controller
    438
    
    Clocks
    439
    
    Resets
    440
  - Scan Manager Module Registers Address Map
    441
  - Document Revision History
    448
System Interconnect

449
- Features of the System Interconnect
  449
- System Interconnect Block Diagram and System Integration
  450
  - Main Connectivity Matrix
    451
- Functional Description of the Interconnect
  452
  - System Interconnect Address Spaces
    453
  - Master Caching and Buffering Overrides
    461
  - Security
    462
  - Cyclic Dependency Avoidance Schemes
    463
  - System Interconnect Master Properties
    464
  - Interconnect Slave Properties
    465
  - Upsizing Data Width Function
    468
  - Downsizing Data Width Function
    469
  - Lock Support
    470
  - System Interconnect Resets
    471
  - Document Revision History
    582
HPS-FPGA Bridges

583
Cortex-A9 Microprocessor Unit Subsystem

637
- Features of the Cortex-A9 MPU Subsystem
  637
- Cortex-A9 MPU Subsystem Block Diagram and System Integration
  638
  - Cortex-A9 MPU Subsystem Internals
    639
  - Cortex-A9 Mpcore
    640
  - Implementation Details
    641
  - Cortex-A9 Processor
    642
  - Interactive Debugging Features
    643
  - Floating Point Unit
    644
  - Memory Management Unit
    645
  - Performance Monitoring Unit
    648
  - Generic Interrupt Controller
    649
  - Global Timer
    661
  - Snoop Control Unit
    662
  - Accelerator Coherency Port
    663
- ACP ID Mapper
  667
  - Implementation Details
    668
  - ACP ID Mapper Address Map and Register Definitions
    673
- L2 Cache
  697
- CPU Prefetch
  704
  - Event Trace
    705
  - Clocks
    706
  - Cortex-A9 MPU Subsystem Address Map
    707
  - L2 Cache Controller Address Map
    708
  - Document Revision History
    709
Coresight Debug and Trace

712
SDRAM Controller Subsystem

739
- Features of the SDRAM Controller Subsystem
  739
- SDRAM Controller Subsystem Block Diagram
  740
- SDRAM Controller Memory Options
  741
- SDRAM Controller Subsystem Interfaces
  742
  - CSR Interface
    743
- Memory Controller Architecture
  744
  - Multi-Port Front End
    745
  - Single-Port Controller
    746
- Functional Description of the SDRAM Controller Subsystem
  748
  - MPFE SDRAM Burst Scheduling
    751
  - Single-Port Controller Operation
    752
  - Memory Protection
    757
- SDRAM Power Management
  762
  - DDR Calibration
    763
  - Resets
    764
  - Initialization
    765
  - FPGA-To-SDRAM Protocol Details
    766
- SDRAM Controller Subsystem Programming Model
  770
  - HPS Memory Interface Simulation
    771
- Debugging HPS SDRAM in the Preloader
  773
- SDRAM Controller Address Map and Register Definitions
  779
- Document Revision History
  815
On-Chip Memory

817
- On-Chip RAM
  817
  - Functional Description of the On-Chip RAM
    818
- Boot ROM
  819
- On-Chip Memory Address Map and Register Definitions
  820
NAND Flash Controller

822
- NAND Flash Controller Features
  822
- NAND Flash Controller Block Diagram and System Integration
  823
- Functional Description of the NAND Flash Controller
  824
  - Bootstrap Interface
    825
  - Configuration by Host
    826
    
    Local Memory Buffer
    827
    
    Resets
    828
  - Command Mapping
    829
  - Data DMA
    835
- NAND Flash Controller Programming Model
  842
  - Basic Flash Programming
    843
  - Flash-Related Special Function Operations
    846
- NAND Flash Controller Address Map and Register Definitions
  854
  - NAND Flash Controller Module Registers (AXI Slave) Address Map
    855
    
    Dma Registers
    859
    
    Document Revision History
    945
SD/MMC Controller

947
- Features of the SD/MMC Controller
  947
  - SD Card Support Matrix
    948
  - MMC Support Matrix
    949
- SD/MMC Controller Signal Description
  950
- Functional Description of the SD/MMC Controller
  951
  - Error Detection
    980
  - Clocks
    981
  - Resets
    982
  - Voltage Switching
    983
- SD/MMC Controller Programming Model
  985
  - Initialization †
    987
  - Controller/Dma/Fifo Buffer Reset Usage
    993
  - Data Transfer Commands
    995
  - Transfer Stop and Abort Commands
    1002
  - Internal DMA Controller Operations
    1004
  - Commands for SDIO Card Devices
    1006
  - CE-ATA Data Transfer Commands
    1008
  - Card Read Threshold
    1016
  - Interrupt and Error Handling
    1019
  - Booting Operation for Emmc and MMC
    1020
- SD/MMC Controller Address Map and Register Definitions
  1030
- Document Revision History
  1089
Quad SPI Flash Controller

1090
- Features of the Quad SPI Flash Controller
  1090
- Quad SPI Flash Controller Block Diagram and System Integration
  1091
- Interface Signals
  1092
  - Data Slave Interface
    1093
  - SPI Legacy Mode
    1096
  - Register Slave Interface
    1097
  - DMA Peripheral Request Controller
    1098
  - Arbitration between Direct/Indirect Access Controller and STIG
    1099
  - XIP Mode
    1101
  - Resets
    1102
- Quad SPI Flash Controller Programming Model
  1103
- Quad SPI Flash Controller Address Map and Register Definitions
  1108
  - QSPI Flash Controller Module Registers Address Map
    1109
  - QSPI Flash Module Data (AHB Slave) Address Map
    1150
DMA Controller

1152
- Features of the DMA Controller
  1152
- DMA Controller Block Diagram and System Integration
  1154
  - AXI Characteristics for a DMA Transfer
    1155
  - Operating States
    1156
  - Initializing the DMAC
    1159
  - Using the Slave Interfaces
    1160
  - Peripheral Request Interface
    1161
  - Using Events and Interrupts
    1172
  - Aborts
    1174
  - Security Usage
    1177
  - Programming Restrictions
    1180
  - Constraints and Limitations of Use
    1184
- DMA Controller Programming Model
  1185
  - Instructions
    1186
  - Assembler Directives
    1201
  - MFIFO Buffer Usage Overview
    1203
- DMA Controller Address Map and Register Definitions
  1211
  - Address Map and Register Definitions
    1213
  - Document Revision History
    1214

Altera Cyclone V Device Handbook (1077 pages)

Brand: Altera | Category: Computer Hardware | Size: 7.66 MB

Volume 1: Device Interfaces and Integration

2
- Table of Contents
  2
- Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices
  
  10
  - Lab
    10
    
    Mlab
    11
    
    Local and Direct Link Interconnects
    12
    
    LAB Control Signals
    13
    
    ALM Resources
    14
    
    ALM Output
    15
  - ALM Operating Modes
    16
    
    Normal Mode
    17
    
    Extended LUT Mode
    17
    
    Arithmetic Mode
    17
    
    Shared Arithmetic Mode
    18
    
    Normal Mode
    18
  - Document Revision History
    20
- Embedded Memory Blocks in Cyclone V Devices
  
  21
- Variable Precision DSP Blocks in Cyclone V Devices
  
  39
  - Features
    39
  - Supported Operational Modes in Cyclone V Devices
    40
  - Resources
    41
  - Design Considerations
    42
    
    Operational Modes
    42
    
    Internal Coefficient and Pre-Adder
    42
    
    Accumulator
    42
    
    Chainout Adder
    42
  - Block Architecture
    43
    
    Input Register Bank
    44
    
    Pre-Adder
    46
    
    Internal Coefficient
    46
    
    Multipliers
    46
    
    Adder
    47
    
    Accumulator and Chainout Adder
    47
    
    Systolic Registers
    48
    
    Double Accumulation Register
    48
    
    Output Register Bank
    48
  - Operational Mode Descriptions
    48
    
    Independent Multiplier Mode
    49
    
    Independent Complex Multiplier Mode
    51
    
    Multiplier Adder Sum Mode
    53
    
    18 X 18 Multiplication Summed with 36-Bit Input Mode
    53
    
    Systolic FIR Mode
    53
  - Document Revision History
    56
- Clock Networks and Plls in Cyclone V Devices
  
  58
  - Clock Networks
    58
    
    Clock Resources in Cyclone V Devices
    59
    
    Types of Clock Networks
    60
    
    Clock Sources Per Quadrant
    64
    
    Types of Clock Regions
    65
    
    Clock Network Sources
    66
    
    Clock Output Connections
    68
    
    Clock Control Block
    68
    
    Clock Power down
    71
    
    Clock Enable Signals
    71
  - Cyclone V Plls
    73
    
    PLL Physical Counters in Cyclone V Devices
    73
    
    PLL Locations in Cyclone V Devices
    74
    
    PLL Migration Guidelines
    79
    
    Fractional PLL Architecture
    79
    
    PLL Cascading
    80
    
    PLL External Clock I/O Pins
    80
    
    PLL Control Signals
    81
    
    Clock Feedback Modes
    82
    
    Clock Multiplication and Division
    88
    
    Programmable Phase Shift
    89
    
    Programmable Duty Cycle
    89
    
    Clock Switchover
    89
    
    PLL Reconfiguration and Dynamic Phase Shift
    94
  - Document Revision History
    95
- I/O Features in Cyclone V Devices
  
  98
- External Memory Interfaces in Cyclone V Devices
  
  175
  - External Memory Performance
    176
  - HPS External Memory Performance
    176
  - Memory Interface Pin Support in Cyclone V Devices
    176
    
    Guideline: Using DQ/DQS Pins
    177
    
    DQ/DQS Bus Mode Pins for Cyclone V Devices
    177
    
    DQ/DQS Groups in Cyclone V E
    179
    
    DQ/DQS Groups in Cyclone V GX
    181
    
    DQ/DQS Groups in Cyclone V GT
    183
    
    DQ/DQS Groups in Cyclone V SE
    185
    
    DQ/DQS Groups in Cyclone V SX
    185
    
    DQ/DQS Groups in Cyclone V ST
    186
  - External Memory Interface Features in Cyclone V Devices
    186
    
    Uniphy IP
    186
    
    External Memory Interface Datapath
    187
    
    DQS Phase-Shift Circuitry
    187
    
    PHY Clock (PHYCLK) Networks
    195
    
    DQS Logic Block
    198
    
    Dynamic OCT Control
    200
    
    IOE Registers
    200
    
    Delay Chains
    202
    
    I/O and DQS Configuration Blocks
    203
  - Hard Memory Controller
    204
    
    Features of the Hard Memory Controller
    204
    
    Multi-Port Front End
    206
    
    Bonding Support
    207
    
    Hard Memory Controller Width for Cyclone V E
    209
    
    Hard Memory Controller Width for Cyclone V GX
    210
    
    Hard Memory Controller Width for Cyclone V GT
    211
    
    Hard Memory Controller Width for Cyclone V SE
    211
    
    Hard Memory Controller Width for Cyclone V SX
    212
    
    Hard Memory Controller Width for Cyclone V ST
    212
  - Document Revision History
    213
- Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
  
  216
  - Enhanced Configuration and Configuration Via Protocol
    216
  - MSEL Pin Settings
    217
  - Configuration Sequence
    218
    
    Power up
    219
    
    Reset
    219
    
    Configuration
    219
    
    Configuration Error Handling
    220
    
    Initialization
    221
    
    User Mode
    221
  - Device Configuration Pins
    221
    
    Configuration Pin Options in the Quartus II Software
    223
  - Fast Passive Parallel Configuration
    224
    
    Fast Passive Parallel Single-Device Configuration
    224
    
    Fast Passive Parallel Multi-Device Configuration
    225
  - Active Serial Configuration
    227
    
    DATA Clock (DCLK)
    227
    
    Active Serial Single-Device Configuration
    228
    
    Active Serial Multi-Device Configuration
    229
    
    Estimating the Active Serial Configuration Time
    230
  - Using EPCS and EPCQ Devices
    230
    
    Controlling EPCS and EPCQ Devices
    231
    
    Trace Length and Loading
    231
    
    Programming EPCS and EPCQ Devices
    231
  - Passive Serial Configuration
    235
    
    Passive Serial Single-Device Configuration Using an External Host
    236
    
    Passive Serial Single-Device Configuration Using an Altera Download Cable
    236
    
    Passive Serial Multi-Device Configuration
    237
  - JTAG Configuration
    239
    
    JTAG Single-Device Configuration
    240
    
    JTAG Multi-Device Configuration
    242
    
    CONFIG_IO JTAG Instruction
    242
  - Configuration Data Compression
    243
    
    Enabling Compression before Design Compilation
    243
    
    Enabling Compression after Design Compilation
    243
    
    Using Compression in Multi-Device Configuration
    243
  - Remote System Upgrades
    244
    
    Configuration Images
    245
    
    Configuration Sequence in the Remote Update Mode
    245
    
    Remote System Upgrade Circuitry
    246
    
    Enabling Remote System Upgrade Circuitry
    246
    
    Remote System Upgrade Registers
    247
    
    Remote System Upgrade State Machine
    249
    
    User Watchdog Timer
    249
  - Design Security
    249
    
    ALTCHIP_ID Megafunction
    250
    
    JTAG Secure Mode
    250
    
    Security Key Types
    251
    
    Security Modes
    252
    
    Design Security Implementation Steps
    252
  - Document Revision History
    253
- SEU Mitigation for Cyclone V Devices
  
  254
  - Error Detection Features
    254
  - Configuration Error Detection
    254
  - User Mode Error Detection
    254
  - Specifications
    255
    
    Minimum EMR Update Interval
    255
    
    Error Detection Frequency
    256
    
    CRC Calculation Time
    256
  - Using Error Detection Features in User Mode
    257
    
    Enabling Error Detection
    257
    
    CRC_ERROR Pin
    258
    
    Error Detection Registers
    258
    
    Error Detection Process
    260
    
    Testing the Error Detection Block
    261
  - Document Revision History
    262
- JTAG Boundary-Scan Testing in Cyclone V Devices
  
  263
  - BST Operation Control
    263
    
    Idcode
    263
    
    Supported JTAG Instruction
    265
    
    JTAG Secure Mode
    268
    
    JTAG Private Instruction
    268
  - I/O Voltage for JTAG Operation
    269
  - Performing BST
    269
  - Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
    270
  - Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
    271
  - IEEE Std. 1149.1 Boundary-Scan Register
    271
    
    Boundary-Scan Cells of a Cyclone V Device I/O Pin
    272
  - Document Revision History
    274
- Power Management in Cyclone V Devices
  
  275
  - Power Consumption
    275
    
    Dynamic Power Equation
    275
  - Hot-Socketing Feature
    276
  - Hot-Socketing Implementation
    276
  - Power-Up Sequence
    278
  - Power-On Reset Circuitry
    279
    
    Power Supplies Monitored and Not Monitored by the por Circuitry
    281
  - Document Revision History
    282
Volume 2: Transceivers

284

Altera Cyclone V User Manual (136 pages)

Hard IP for PCI Express

Brand: Altera | Category: Motherboard | Size: 3.95 MB

Table of Contents
3
Chapter 1. Datasheet

7
- Features
  7
- Release Information
  9
- Device Family Support
  9
- Configurations
  9
- Debug Features
  10
- IP Core Verification
  11
- Performance and Resource Utilization
  11
- Recommended Speed Grades
  11
Chapter 2. Getting Started

13
Chapter 3. Parameter Settings

33
- System Settings
  33
- Port Functions
  35
  - Parameters Shared Across All Port Functions
    35
    
    Device
    36
    
    Error Reporting
    37
    
    Link
    38
    
    Slot
    38
    
    Power Management
    39
  - Parameters Defined Separately for All Port Functions
    39
    
    Base Address Registers for Function <N
    39
    
    Base and Limit Registers for Root Port Func <N
    39
    
    Device ID Registers for Function <N
    39
    
    PCI Express/Pci Capabilities for Func <N
    39
Chapter 4. IP Core Architecture

43
- Key Interfaces
  44
  - Avalon-ST Interface
    44
    
    RX Datapath
    44
    
    TX Datapath
    44
  - Clocks and Reset
    45
  - Local Management Interface (LMI Interface)
    45
  - Interrupts
    45
- Protocol Layers
  46
  - Transaction Layer
    46
    
    Configuration Space
    47
  - Data Link Layer
    48
  - Physical Layer
    49
- Multi-Function Support
  52
Chapter 5. IP Core Interfaces

54
- Avalon-ST RX Interface
  55
  - Data Alignment and Timing for the 64-Bit Avalon-ST RX Interface
    57
- Avalon-ST TX Interface
  60
- ECRC Forwarding
  66
- Clock Signals
  66
- Reset Signals
  66
- ECC Error Signals
  69
- Interrupts for Endpoints
  69
- Interrupts for Root Ports
  70
- Completion Side Band Signals
  71
- Transaction Layer Configuration Space Signals
  72
  - Configuration Space Register Access Timing
    75
  - Configuration Space Register Access
    76
- LMI Signals
  79
  - LMI Read Operation
    81
  - LMI Write Operation
    81
- Power Management Signals
  82
- Physical Layer Interface Signals
  84
  - Transceiver Reconfiguration
    84
  - Serial Interface Signals
    84
  - PIPE Interface Signals
    85
- Test Signals
  88

Altera Cyclone V Reference Manual (66 pages)

GT FPGA Development Board

Brand: Altera | Category: Motherboard | Size: 1.77 MB

Table of Contents
3
Chapter 1. Overview

5
Chapter 2. Board Components

10
- Board Overview
  10
- Featured Device: Cyclone V GT FPGA
  13
  - I/O Resources
    13
- MAX V CPLD 5M2210 System Controller
  14
- Configuring the MAX V Device to Program EPCQ
  19
- FPGA Configuration
  19
- Status Elements
  23
- Setup Elements
  25
- Clock Circuitry
  27
  - On-Board Oscillators
    27
  - Off-Board Clock Input/Output
    29
- General User Input/Output
  30
  - User-Defined Push Buttons
    30
  - User-Defined DIP Switch
    31
  - User-Defined Leds
    31
    
    General Leds
    31
    
    HSMC Leds
    32
    
    PCI Express Leds
    32
  - Character LCD
    33
- Components and Interfaces
  33
  - PCI Express
    33
  - 10/100/1000 Ethernet
    35
  - Hsmc
    37
  - SDI Channel (Optional)
    43
    
    SDI Video Output
    44
    
    SDI Video Input
    45
- Memory
  46
  - Ddr3 Sdram
    46
    
    Ddr3A
    46
    
    Ddr3B
    51
  - Flash
    57
- Power Supply
  58
  - Power Distribution System
    59
  - Power Measurement
    60

Altera Cyclone V Boot Manual (30 pages)

HPS SoC

Brand: Altera | Category: Microcontrollers | Size: 1.03 MB

Altera Categories

Motherboard Microcontrollers Computer Hardware Transceiver Recording Equipment

More Altera Manuals

Altera Cyclone V Manuals

Altera Cyclone V Technical Reference (3536 pages)

Table of Contents

Introduction to the Hard Processor System

Clock Manager

Reset Manager

FPGA Manager

System Manager

Scan Manager

System Interconnect

HPS-FPGA Bridges

Cortex-A9 Microprocessor Unit Subsystem

Coresight Debug and Trace

SDRAM Controller Subsystem

On-Chip Memory

NAND Flash Controller

SD/MMC Controller

Quad SPI Flash Controller

DMA Controller

Altera Cyclone V Device Handbook (1077 pages)

Table of Contents

Volume 1: Device Interfaces and Integration

Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

Embedded Memory Blocks in Cyclone V Devices

Variable Precision DSP Blocks in Cyclone V Devices

Clock Networks and Plls in Cyclone V Devices

I/O Features in Cyclone V Devices

External Memory Interfaces in Cyclone V Devices

Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices

SEU Mitigation for Cyclone V Devices

JTAG Boundary-Scan Testing in Cyclone V Devices

Power Management in Cyclone V Devices

Volume 2: Transceivers

Transceiver Architecture in Cyclone V Devices

Transceiver Clocking in Cyclone V Devices

Transceiver Reset Control in Cyclone V Devices

Transceiver Protocol Configurations in Cyclone V Devices

Transceiver Loopback Support

Dynamic Reconfiguration in Cyclone V Devices

Altera Cyclone V User Manual (136 pages)

Table of Contents

Chapter 1. Datasheet

Chapter 2. Getting Started

Chapter 3. Parameter Settings

Chapter 4. IP Core Architecture

Chapter 5. IP Core Interfaces

Altera Cyclone V Reference Manual (66 pages)

Table of Contents

Chapter 1. Overview

Chapter 2. Board Components

Altera Cyclone V Boot Manual (30 pages)

Related Products

Altera Categories