Altera cyclone V Technical Reference page 261

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
l3master Fields
Bit
3
hprotcache_0
2
hprotbuff_0
1
hprotpriv_0
0
hprotdata_0
NAND Flash Controller Register Group Register Descriptions
Registers related to NAND Flash Controller which aren't located in the NAND Flash Controller itself.
Offset:
0x110
bootstrap
Bootstrap fields sampled by NAND Flash Controller when released from reset. All fields are reset by a cold
or warm reset.
l3master
on page 5-69
Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated
only during system initialization prior to removing the peripheral from reset. They may not be changed
dynamically during peripheral operation All fields are reset by a cold or warm reset.
System Manager
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
If 1, L3 master accesses for the SD/MMC module are
cacheable.
If 1, L3 master accesses for the SD/MMC module are
bufferable.
If 1, L3 master accesses for the SD/MMC module are
privileged.
Specifies if the L3 master access is for data or opcode
for the SD/MMC module.
0x0
0x1
on page 5-68
NAND Flash Controller Register Group Register Descriptions
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Value Description
Opcode fetch
Data access
21 20 19 18
5 4 3 2
hprot hprot
cache buff_
_0 0
RW RW
0x0 0x0
Access
RW
RW
RW
RW
5-67
17 16
1 0
hprot hprotdat
priv_ a_0
0
RW 0x1
RW
0x1
Reset
0x0
0x0
0x1
0x1
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