Altera cyclone V Technical Reference page 488

7-40
l4mp
Bit
2
i2c0
1
sptimer0
0
sdrregs
l4mp
Controls security settings for L4 MP peripherals.
Module Instance
l3regs
Offset:
0x10
Access:
WO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
Controls whether secure or non-secure masters can
access the I2C0 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the SP Timer 0 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the SDRAM Registers slave.
Value
0x0
0x1
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Base Address
Access
Register Address
0xFF800010
System Interconnect
cv_5v4
2016.10.28
Reset
WO 0x0
WO 0x0
WO 0x0
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