Altera cyclone V Technical Reference page 283

cv_5v4
2016.10.28
31 30
15 14
sdmmc Fields
Bit
8
derrportb
7
serrportb
6
derrporta
5
serrporta
4
injdportb
3
injsportb
System Manager
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29 28 27 26
13 12 11 10
Reserved
Name
This bit is an interrupt status bit for SDMMC Port B
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in SDMMC Port B RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for SDMMC Port B
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
SDMMC Port B RAM. Software needs to write 1 into
this bit to clear the interrupt status.
This bit is an interrupt status bit for SDMMC Port A
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in SDMMC Port A RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for SDMMC Port A
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
SDMMC Port A RAM. Software needs to write 1 into
this bit to clear the interrupt status.
Changing this bit from zero to one injects a double,
non-correctable error into the SDMMC RAM at Port
B. This only injects one double bit error into the
SDMMC RAM at Port B.
Changing this bit from zero to one injects a single,
correctable error into the SDMMC RAM at Port B.
This only injects one error into the SDMMC RAM at
Port B.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
derrp serrp derrp
ortb ortb orta
RW RW RW
0x0 0x0 0x0
Description
sdmmc
21 20 19 18
5 4 3 2
serrp injdp injsp injdp
orta ortb ortb orta
RW RW RW RW
0x0 0x0 0x0 0x0
Access
5-89
17 16
1 0
injsp en
orta
RW 0x0
RW
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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