Coresight Debug And Trace Programming Model - Altera cyclone V Technical Reference

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CoreSight Debug and Trace Programming Model

ARM Reset Name
nPOTRST
nTRST
TRESETn
The ETR stall enable field (
ETR is requested to stall its AXI master interface to the L3 interconnect before a warm or debug reset.
The level 4 (L4) watchdog timers can be paused during debugging to prevent reset while the processor is
stopped at a breakpoint.
Related Information
Reset Manager
•
• Watchdog Timer
• ARM Infocenter
For more information about the CoreSight port names, refer to the CoreSight Technology System Design
Guide.
CoreSight Debug and Trace Programming Model
This section describes programming model details specific to Altera's implementation of the ARM
CoreSight technology.
The debug components can be configured to cause triggers when certain events occur. For example, soft
logic in the FPGA fabric can signal an event which triggers an STM message injection into the trace
stream.
Related Information
ARM Infocenter
Programming interface details of each CoreSight component.
Coresight Component Address
CoreSight components are configured through memory-mapped registers, located at offsets relative to the
CoreSight component base address. CoreSight component base addresses are accessible through the
component address table in the DAP ROM.
Table 10-7: Coresight Component Address Table
The following table is located in the ROM table portion of the DAP.
Altera Corporation
Clock Source
Reset manager
tap_cold_rst_n
JTAG interface
nTRST
Reset manager
dbg_rst_n
etrstallen
on page 3-1
on page 24-1
HPS Reset Signal Name
pin
) of the register in the reset manager controls whether the
ctrl
Description
True power on reset signal to the
DAP SWJ-DP. It must only reset at
power-on.
Resets the DAP TAP controller
inside the SWJ-DP. This signal is
driven by the host using the JTAG
connector.
Reset signal for TPIU. Resets all
registers in the
TRACECLKIN
domain.
CoreSight Debug and Trace
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cv_5v4
2016.10.28