Altera cyclone V Technical Reference page 605

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
periph_id_0 Fields
Bit
7:0
pn7to0
periph_id_1
Peripheral ID1
Module Instance
hps2fpgaregs
Offset:
0x1FE4
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
HPS-FPGA Bridges
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Part Number [7:0]
0xFF500000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
periph_id_1
21 20 19 18
5 4 3 2
pn7to0
RO 0x1
Access
Register Address
0xFF501FE4
21 20 19 18
5 4 3 2
jep3to0_pn11to8
RO 0xB3
8-23
17 16
1 0
Reset
RO 0x1
17 16
1 0
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