Mpu L2 Cache Controller (L2C-310) Module Address Map - Altera cyclone V Technical Reference

10-26

MPU L2 Cache Controller (L2C-310) Module Address Map

Module Instance
Reserved
Interrupt
Distributor
Reserved
MPU L2 Cache Controller (L2C-310) Module Address Map
This address space is allocated to the MPU L2 cache controller. For detailed information about the use of
this address space,
Table 10-19: MPU L2 Cache Controller Address Range
Module Instance
MPUL2
Table 10-20: MPU L2 Cache Controller Register Range
Register Group
Cache ID and
Cache Type
Control
Interrupt/
Counter Control
Reserved
Cache
Maintenance
Operations
Altera Corporation
Description
This address space is
reserved.
Caution: Any access to
this region causes a
SLVERR abort
exception.
This address space is
allocated for the
interrupt distributor.
This address space is
reserved.
click here to access the ARM documentation for the L2C-310.
0xFFFEF000
Description
This address space is
allocated for the cache
ID and cache type
registers.
This is the address
space for the cache
control registers.
This address space is
allocated for the
Interrupt/Counter
control registers.
This address space is
reserved.
This is the address
space is allocated for
the cache maintenance
operation registers.
Start Address
0xFFFEC700
0xFFFED000
0xFFFEE000
Start Address
Start Address
0xFFFEF000
0xFFFEF100
0xFFFEF200
0xFFFEF300
0xFFFEF700
End Address
0xFFFEC7FF
0xFFFEDFFF
0xFFFEEFFF
End Address
0xFFFEFFFF
End Address
0xFFFEF0FF
0xFFFEF1FF
0xFFFEF2FF
0xFFFEF6FF
0xFFFEF7FF
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cv_5v4
2016.10.28