Altera cyclone V Technical Reference page 137

3-26
permodrst
Offset:
0x14
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30 29
Reserved sdr
RW
0x1
15 14 13
i2c3 i2c2 i2c1
RW RW RW
0x1 0x1 0x1
permodrst Fields
Bit
29
sdr
28
dma
27
gpio2
26
gpio1
25
gpio0
24
can1
23
can0
22
sdmmc
21
spis1
20
spis0
19
spim1
18
spim0
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
28 27 26
dma gpio2 gpio1 gpio0
RW RW RW
0x1 0x1 0x1
12 11 10
i2c0 sptim sptim osc1t
er1 er0 imer1
RW
0x1 RW RW
0x1 0x1
Name
Resets SDRAM Controller Subsystem affected by a
warm or cold reset.
Resets DMA controller
Resets GPIO2
Resets GPIO1
Resets GPIO0
Resets CAN1 controller. Writes to this field on devices
not containing CAN controllers will be ignored.
Resets CAN0 controller. Writes to this field on devices
not containing CAN controllers will be ignored.
Resets SD/MMC controller
Resets SPIS1 controller
Resets SPIS0 controller
Resets SPIM1 controller
Resets SPIM0 controller
Bit Fields
25 24 23 22
can1 can0 sdmmc
RW RW RW RW
0x1 0x1 0x1 0x1
9 8 7 6
osc1t l4wd1 l4wd0
imer0
RW RW
RW RW 0x1 0x1
0x1 0x1
Description
21 20 19 18
spis1 spis0 spim1 spim0
RW RW RW RW
0x1 0x1 0x1 0x1
5 4 3 2
qspi nand usb1 usb0
RW RW RW RW
0x1 0x1 0x1 0x1
cv_5v4
2016.10.28
17 16
uart1 uart0
RW RW 0x1
0x1
1 0
emac1 emac0
RW RW 0x1
0x1
Access Reset
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
Reset Manager
Send Feedback