Altera cyclone V Technical Reference page 909

Hard processor system
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13-88
onfi_device_no_of_blocks_per_lun_l
Module Instance
nandregs
Offset:
0x3C0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
onfi_device_no_of_luns Fields
Bit
8
onfi_device
7:0
no_of_luns
onfi_device_no_of_blocks_per_lun_l
Lower bits of number of blocks per LUN present in the ONFI complaint device.
Module Instance
nandregs
Offset:
0x3D0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Name
Indicates if the device is an ONFI compliant device.
[list] [*]0 - Non-ONFI compliant device [*]1 - ONFI
compliant device[/list]
Indicates the number of LUNS present in the device
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
0xFFB80000
Bit Fields
25
24
23
22
Reserved
9
8
7
6
onfi_
devic
e
RW
0x0
Description
Base Address
0xFFB80000
Register Address
0xFFB803C0
21
20
19
18
5
4
3
2
no_of_luns
RO 0x0
Access
Register Address
0xFFB803D0
NAND Flash Controller
cv_5v4
2016.10.28
17
16
1
0
Reset
RW
0x0
RO
0x0
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