Altera cyclone V Technical Reference page 97

2-60
gpiodiv
Bit
2:0
usbclk
gpiodiv
Contains a field that controls the clock divider for the GPIO De-bounce clock. Only reset by a cold reset.
Module Instance
clkmgr
Offset:
0xA8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
The usb_mp_clk is divided down from the periph_
base_clk by the value specified in this field.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
Description
Value
Divide By 1
Divide By 2
Divide By 4
Divide By 8
Divide By 16
Reserved
Reserved
Reserved
Base Address
0xFFD04000
Bit Fields
25 24 23 22
9 8 7 6
gpiodbclk
RW 0x1
Description
Register Address
0xFFD040A8
21 20 19
gpiodbclk
RW 0x1
5 4 3
cv_5v4
2016.10.28
Access Reset
RW 0x0
18 17 16
2 1 0
Clock Manager
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