Altera cyclone V Technical Reference page 238

5-44
EMAC Group Register Descriptions
Bit
0
vio1req
EMAC Group Register Descriptions
External control registers for the EMACs
Offset:
0x60
ctrl
on page 5-44
Registers used by the EMACs. All fields are reset by a cold or warm reset.
l3master on page 5-46
Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated
only during system initialization prior to removing the peripheral from reset. They may not be changed
dynamically during peripheral operation All fields are reset by a cold or warm reset.
ctrl
Registers used by the EMACs. All fields are reset by a cold or warm reset.
Module Instance
sysmgr
Offset:
0x60
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
Requests hardware state machine to generate freeze
signal sequence to transition between frozen and
thawed states. If this field is read by software, it
contains the value previously written by software (i.e.
this field is not written by hardware).
Value
0x0
0x1
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Requests a thaw (unfreeze) operation.
Requests a freeze operation.
Base Address
Access
Register Address
0xFFD08060
cv_5v4
2016.10.28
Reset
RW 0x1
System Manager
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