Global Timer - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
GIC Source Block
Interrupt
Number
207 FPGA
manager
208 CoreSight
209 CoreSight
210 On-chip RAM
211 On-chip RAM
Related Information
Implementation Details

Global Timer

The MPU features a global 64-bit, auto-incrementing timer, which is primarily used by the operating
system.
Functional Description
The global timer is accessible by the processors using memory-mapped access through the SCU. The
global timer has the following features:
• 64-bit incrementing counter with an auto-incrementing feature. It continues incrementing after
sending interrupts.
• Memory-mapped in the private memory region.
• Accessed at reset in Secure State only. It can only be set once, but secure code can read it at any time.
• Accessible to both Cortex-A9 processors in the MPCore.
• Clocked by
Implementation Details
Each Cortex-A9 processor has a private 64-bit comparator that generates a private interrupt when the
counter reaches the specified value. Each Cortex-A9 processor uses the banked ID, ID27, for this
interrupt. ID27 is sent to the GIC as a Private Peripheral Interrupt (PPI).
The global timer is clocked by mpu_periph_clk, running at ¼ the rate of mpu_clk.
Related Information
ARM Infocenter
For more information about the global timer, refer to "About the Global Timer" in the Global timer, Private
timers, and Watchdog registers chapter of the Cortex-A9 MPCore Technical Reference Manual, available on
the ARM Infocenter website.
Cortex-A9 Microprocessor Unit Subsystem
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Interrupt Name
fpga_man_IRQ
nCTIIRQ[0]
nCTIIRQ[1]
ram_ecc_corrected_IRQ
ram_ecc_uncorrected_IRQ
on page 9-13
, running at ¼ the rate of
mpu_periph_clk
Combined Interrupts
This interrupt combines:
through
man_irq[7] fpga_man_
.
irq[0]
—
—
—
—
.
mpu_clk
9-25
Global Timer
Triggering
Level
fpga_
Level
Level
Level
Level
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