Altera cyclone V Technical Reference page 178

cv_5v4
2016.10.28
Bit
7
prd
6
pre
5
prr
4
ccd
3
crc
2
id
FPGA Manager
Send Feedback
Name
Controls the polarity of edge or level sensitivity for
PR_DONE
Value
0x0
0x1
Controls the polarity of edge or level sensitivity for
PR_ERROR
Value
0x0
0x1
Controls the polarity of edge or level sensitivity for
PR_READY
Value
0x0
0x1
Controls the polarity of edge or level sensitivity for
CVP_CONF_DONE
Value
0x0
0x1
Controls the polarity of edge or level sensitivity for
CRC_ERROR
Value
0x0
0x1
Controls the polarity of edge or level sensitivity for
INIT_DONE
Value
0x0
0x1
Description
Description
Active low
Active high
Description
Active low
Active high
Description
Active low
Active high
Description
Active low
Active high
Description
Active low
Active high
Description
Active low
Active high
4-35
gpio_int_polarity
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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