Altera cyclone V Technical Reference page 150

cv_5v4
2016.10.28
Note: You must set the
enters the reset phase.
Configuration Phase
To configure the FPGA using the HPS, software sets the
then sends configuration data to the FPGA by writing data to the write data register (
manager module configuration data address map. Software polls the
gpio_instatus
successful, software sets the
stated in this phase.
After successfully completing the configuration phase, the FPGA transitions to the initialization phase. To
delay configuring the FPGA, set the
Related Information
Booting and Configuration
Initialization Phase
In this phase, the FPGA prepares to enter user mode. The internal oscillator in the FPGA portion of the
device is the default clock source for the initialization phase. Alternatively, the configuration image can
specify the
FPGA enters user mode.
If is selected as the clock source, software uses the
DCLK
to the FPGA. Writing to the
specified number of
status (
dclkstat
have been sent.
Note: Before another write to the
bit to clear the done state.
The FPGA user I/O pins are still tri-stated in this phase. When the initialization phase completes, the
FPGA releases the optional
User Mode
The FPGA enters the user mode after exiting the initialization phase. The FPGA user I/O pins are no
longer tri-stated in this phase and the configured soft logic in the FPGA becomes active.
The FPGA remains in user mode until the
FPGA reenters the reset phase. The internal oscillator is disabled in user mode, but is enabled as soon as
the
nCONFIG
Related Information
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
•
For more information about configuring the FPGA through the HPS, refer to the "Configuration,
Design Security, and Remote System Upgrade in Cyclone V Devices" appendix in the Cyclone V Device
Handbook Volume 1: Device Interfaces and Integration.
• Booting and Configuration
FPGA Manager
Send Feedback
and
cdratio
register to determine if the FPGA configuration is successful. When configuration is
axicfgen
on page 30-1
or the pins as the clock source. The alternate clock source controls when the
CLKUSR DCLK
field of the
cnt
pulses. When all of the
DCLK
) register is set to 1. Software polls the
dclkcnt
INIT_DONE
pin is driven low.
on page 30-1
bits of the
cfgwdth ctrl
axicfgen
bit of the register to 0. The FPGA user I/O pins are still tri-
ctrl
bit of the
confdonepull
DCLK
register triggers the FPGA manager to generate the
dclkcnt
pulses have been sent, the
DCLK
dcntdone
register, software needs to write a value of 1 to the
pin and an external resistor pulls the pin high.
pin is driven low. If the
nCONFIG
Configuration Phase
register appropriately before the FPGA
bit of the register to 1. Software
ctrl
data
pin by reading the
CONF_DONE
register to 1.
ctrl
count ( ) register to drive
dclkcnt
dcntdone
bit to know when all of the
pin is driven low, the
nCONFIG
4-7
) in the FPGA
pulses
DCLK
bit of the
DCLK
pulses
DCLK
dcntdone
Altera Corporation