Altera cyclone V Technical Reference page 816

11-78
Document Revision History
Date
November 2015
May 2015
December 2014
June 2014
December 2013
November 2012
January 2012
Altera Corporation
Version
2015.11.02
• Added information regarding calculation of ECC error byte address
location from
sectoin
• Added information regarding bus response to memory protection
transaction failure in "Memory Protection" section
• Clarified "Protection" row in "Fields for Rules in Memory
Protection" table in the "Memory Protection" section
• Clarified protruledata.security column in "Rules in Memory
Protection Table for Example Configuration" table in the "Example
of Configuration for TrustZone" section
• Added note about double-bit error functionality in "ECC Write
Backs" subsection of "ECC" section
• Added the "DDR Calibration" subsection under "DDR PHY"
section
2015.05.04
• Added the recommended sequence for writing or reading a rule in
the "Memory Protection" section.
2014.12.15
• Added SDRAM Protection Access Flow Diagram to "Memory
Protection" subsection in the "Single-Port Controller Operation"
section.
• Changed the "SDRAM Multi-Port Scheduling" section to "SDRAM
Multi-Port Arbitration" and added detailed information on how to
use and program the priority and weighted arbitration scheme.
2014.6.30
• Added Port Mappings section.
• Added SDRAM Controller Memory Options section.
• Enhanced Example of Configuration for TrustZone section.
• Added SDRAM Controller address map and registers.
2013.12.30
• Added Generating a Preloader Image for HPS with EMIF section.
• Added Debugging HPS SDRAM in the Preloader section.
• Enhanced Simulation section.
1.1 Added address map and register definitions section.
1.0 Initial release.
Changes
register in "User Notification of ECC Errors"
erraddr
cv_5v4
2016.10.28
SDRAM Controller Subsystem
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