Usb Otg Controller Programming Model - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
A-Device timeout while waiting for B-Device connection.
Host negotiation is complete.
Session request is complete.
Session end is detected in device mode.

USB OTG Controller Programming Model

For detailed information about using the USB OTG controller, consult your operating system (OS) driver
documentation. The OS vendor provides application programming interfaces (APIs) to control USB host,
device and OTG operation. This section provides a brief overview of the following software operations:
• Enabling SPRAM ECCs
• Host operation
• Device operation
Enabling SPRAM ECCs
To avoid false ECC errors, you must initialize the ECC bits in the SPRAM before using ECCs. To initialize
the ECC bits, software writes data to all locations in the SPRAM.
The L3 interconnect has access to the SPRAM and is accessible through the USB OTG L3 slave interface.
Software accesses the SPRAM through the
space.
The SPRAM contains 8192 (32 KB) locations. The L3 slave provides 32-bit access to the SPRAM.
Physically, the SPRAM is implemented as a 35-bit memory, with the highest three bits reserved for the
USB OTG controller's internal use. When a write is performed to the SPRAM through the L3 slave
interface, bits 32 through 34 of the internal data bus are tied to 1, to enable the ECC bits to be initialized.
Note: Software cannot access the SPRAM beyond the 32-KB range. Out-of-range read transactions return
indeterminate data. Out-of-range write transactions are ignored.
Host Operation
Host Initialization
After power up, the USB port is in its default mode. No VBUS is applied to the USB cable. The following
process sets up the USB OTG controller as a USB host.
1. To enable power to the USB port, the software driver sets the Port Power (
Port Control and Status Register (
drives the V
USB 2.0 OTG Controller
Send Feedback
Condition
hprt
signal on the USB link.
BUS
USB OTG Controller Programming Model
memory space, in the USB OTG controller address
directfifo
) of the Host Mode Registers (
Mode
OTG interrupts
OTG interrupts
OTG interrupts
OTG interrupts
) bit to 1 in the Host
prtpwr
) group. This action
hostgrp
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