Altera cyclone V Technical Reference page 3

Reset Sequencing............................................................................................................................3-11
Reset Pins........................................................................................................................................ 3-15
Reset Effects.................................................................................................................................... 3-15
Altering Warm Reset System Response...................................................................................... 3-15
Reset Handshaking........................................................................................................................ 3-16
Reset Manager Address Map and Register Definitions.........................................................................3-16
Reset Manager Module Address Map......................................................................................... 3-17
Document Revision History.....................................................................................................................3-32
FPGA Manager.................................................................................................... 4-1
Features of the FPGA Manager.................................................................................................................. 4-1
FPGA Manager Block Diagram and System Integration........................................................................4-2
Functional Description of the FPGA Manager........................................................................................ 4-3
FPGA Manager Building Blocks.................................................................................................... 4-3
FPGA Configuration....................................................................................................................... 4-4
FPGA Status......................................................................................................................................4-8
Error Message Extraction................................................................................................................4-8
Boot Handshake............................................................................................................................... 4-8
General Purpose I/O........................................................................................................................4-9
Clock.................................................................................................................................................. 4-9
Reset................................................................................................................................................... 4-9
FPGA Manager Address Map and Register Definitions......................................................................... 4-9
FPGA Manager Module Configuration Data Address Map.......................................................4-9
FPGA Manager Module Address Map........................................................................................4-10
Document Revision History.....................................................................................................................4-51
System Manager...................................................................................................5-1
Features of the System Manager.................................................................................................................5-1
System Manager Block Diagram and System Integration...................................................................... 5-2
Functional Description of the System Manager.......................................................................................5-3
Boot Configuration and System Information.............................................................................. 5-3
Additional Module Control............................................................................................................ 5-3
Boot ROM Code...............................................................................................................................5-6
FPGA Interface Enables.................................................................................................................. 5-8
ECC and Parity Control.................................................................................................................. 5-8
Preloader Handoff Information..................................................................................................... 5-9
Clocks................................................................................................................................................ 5-9
Resets................................................................................................................................................. 5-9
System Manager Address Map and Register Definitions........................................................................5-9
System Manager Module Address Map.........................................................................................5-9
Document Revision History...................................................................................................................5-237
Scan Manager.......................................................................................................6-1
Features of the Scan Manager.....................................................................................................................6-1
Scan Manager Block Diagram and System Integration.......................................................................... 6-2
ARM JTAG-AP Signal Use in the Scan Manager.........................................................................6-2
TOC-3
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