Altera cyclone V Technical Reference page 266

5-72
l3master
Module Instance
sysmgr
Offset:
0x118
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
l3master Fields
Bit
7
hprotcache_1
6
hprotcache_0
5
hprotbuff_1
4
hprotbuff_0
3
hprotpriv_1
2
hprotpriv_0
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
If 1, L3 master accesses for the USB modules are
cacheable. The field array index corresponds to the
USB index.
If 1, L3 master accesses for the USB modules are
cacheable. The field array index corresponds to the
USB index.
If 1, L3 master accesses for the USB modules are
bufferable. The field array index corresponds to the
USB index.
If 1, L3 master accesses for the USB modules are
bufferable. The field array index corresponds to the
USB index.
If 1, L3 master accesses for the USB modules are
privileged. The field array index corresponds to the
USB index.
If 1, L3 master accesses for the USB modules are
privileged. The field array index corresponds to the
USB index.
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
hprot hprot
cache cache
_1 _0
RW RW
0x0 0x0
Description
Register Address
0xFFD08118
21 20 19 18
5 4 3 2
hprot hprot hprot hprot
buff_ buff_ priv_ priv_
1 0 1 0
RW RW RW RW
0x0 0x0 0x1 0x1
cv_5v4
2016.10.28
17 16
1 0
hprot hprotdat
data_ a_0
1
RW 0x1
RW
0x1
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x1
RW 0x1
System Manager
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