Altera cyclone V Technical Reference page 34

1-18
HPS Peripheral Region Address Map
Slave Identifier
LWFPGASLAVES
LWHPS2FPGAREGS
HPS2FPGAREGS
FPGA2HPSREGS
EMAC0
EMAC1
SDMMC
QSPIREGS
FPGAMGRREGS
ACPIDMAP
GPIO0
GPIO1
GPIO2
L3REGS
NANDDATA
QSPIDATA
USB0
USB1
NANDREGS
Altera Corporation
Description
FPGA slaves accessed with
lightweight HPS-to-FPGA
bridge
Lightweight HPS-to-FPGA
bridge global programm‐
er's view (GPV) registers
HPS-to-FPGA bridge GPV
registers
FPGA-to-HPS bridge GPV
registers
Ethernet MAC 0
Ethernet MAC 1
SD/MMC
Quad SPI flash controller
registers
FPGA manager registers
ACP ID mapper registers
GPIO 0
GPIO 1
GPIO 2
L3 interconnect GPV
NAND flash controller
data
Quad SPI flash data
USB 2.0 OTG 0 controller
registers
USB 2.0 OTG 1 controller
registers
NAND flash controller
registers
Base Address
0xFF200000
0xFF400000
0xFF500000
0xFF600000
0xFF700000
0xFF702000
0xFF704000
0xFF705000
0xFF706000
0xFF707000
0xFF708000
0xFF709000
0xFF70A000
0xFF800000
0xFF900000
0xFFA00000
0xFFB00000
0xFFB40000
0xFFB80000
Introduction to the Hard Processor System
2016.10.28
Size
2 MB
1 MB
1 MB
1 MB
8 KB
8 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
1 MB
64 KB
1 MB
256 KB
256 KB
64 KB
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