Interconnect Slave Properties - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Master Width
SD/ 32
MMC
ETR 32
DAP 32
The AXI IDs of the HPS peripheral masters identify transactions from the HPS to soft logic over the HPS-
to-FPGA bridge. Soft logic in the FPGA can monitor the AXI IDs to determine which master issued each
transaction. For HPS peripheral AXI IDs, refer to "HPS Peripheral Master Input IDs".
Related Information
• http://infocenter.arm.com
Additional information about TrustZone security is available from the ARM Infocenter website.
• HPS Peripheral Master Input IDs
For a list of HPS peripheral AXI IDs, refer to the Cortex-A9 Microprocessor Unit Subsystem chapter.

Interconnect Slave Properties

The interconnect connects to various slave interfaces through the L3 interconnect, L3 slave peripheral
switch, and the five L4 peripheral buses. After reset, all slave interfaces are set to the secure state.
The interconnect provides FIFO buffers with clock crossing adapters. Refer to "FIFO Buffers and Clock
Crossing" for details.
Table 7-5: Interconnect Slave Interfaces
Slave
SDRAM 32
subsystem
CSR
(16) Each channel has a dedicated FIFO buffer. This allows the channels to function as independent streams.
Acceptance is based on the number of read, write, and total transactions.
(17)
The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth
(18)
is based on W, A, and D channels.
System Interconnect
Send Feedback
Clock Switch
L3 master
l4_mp_clk
peripheral
switch
L3 master
dbg_at_clk
peripheral
switch
L3
dbg_clk
intercon‐
nect
I/F Width Clock
l4_sp_clk
TrustZone GPV
Security Access
Nonsecur No
e
Per No
Transac‐
tion
Secure Yes
on page 9-34
Mastered By
L4 SP bus master
Interconnect Slave Properties
CDAS Issuance FIFO
Buffer
Depth
6)
SSPID 2, 2, 4 2, 2, 2
SSPID 32, 1, 32 2, 2, 2,
2, 2
SS 1, 1, 1 2, 2, 2
Acceptance Buffer
(17)
Depth
(18)
1, 1, 1 2, 2, 2
Altera Corporation
7-17
Type
(1
AH
B
AXI
AH
B
Type
APB