Altera cyclone V Technical Reference page 624

8-42
comp_id_2
31 30
15 14
comp_id_1 Fields
Bit
7:0
genipcompcls_preamble
comp_id_2
Component ID2
Module Instance
lwhps2fpgaregs
Offset:
0x1FF8
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
comp_id_2 Fields
Bit
7:0
preamble
comp_id_3
Component ID3
Altera Corporation
29 28 27 26
13 12 11 10
Reserved
Name
Generic IP component class, Preamble
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Preamble
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF400000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
21 20 19 18
5 4 3 2
genipcompcls_preamble
RO 0xF0
Access
Register Address
0xFF401FF8
21 20 19 18
5 4 3 2
preamble
RO 0x5
Access
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0xF0
17 16
1 0
Reset
RO 0x5
HPS-FPGA Bridges
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