Altera cyclone V Technical Reference page 912

cv_5v4
2016.10.28
Bit
1:0
n_banks
Interrupt and Status Registers Register Descriptions
Contains interrupt and status registers of controller accessible by software.
Offset:
0x400
transfer_mode
Current data transfer mode is Main only, Spare only or Main+Spare. This information is per bank.
intr_status0
Interrupt status register for bank 0
intr_en0
on page 13-94
Enables corresponding interrupt bit in interrupt register for bank 0
page_cnt0
Decrementing page count bank 0
err_page_addr0
Erred page address bank 0
err_block_addr0
Erred block address bank 0
intr_status1
Interrupt status register for bank 1
intr_en1 on page 13-100
Enables corresponding interrupt bit in interrupt register for bank 1
page_cnt1
Decrementing page count bank 1
err_page_addr1
Erred page address bank 1
err_block_addr1
Erred block address bank 1
intr_status2
Interrupt status register for bank 2
intr_en2
on page 13-105
Enables corresponding interrupt bit in interrupt register for bank 2
page_cnt2
Decrementing page count bank 2
err_page_addr2
Erred page address bank 2
NAND Flash Controller
Send Feedback
Name
Maximum number of banks supported by hardware.
This is an encoded value. [list][*]0 - Two banks [*]1 -
Four banks [*]2 - Eight banks [*]3 - Sixteen banks[/
list]
on page 13-92
on page 13-93
on page 13-96
on page 13-97
on page 13-98
on page 13-98
on page 13-102
on page 13-102
on page 13-103
on page 13-104
on page 13-107
on page 13-108
Interrupt and Status Registers Register Descriptions
Description
13-91
Access Reset
RO 0x1
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