Emac Internal Interfaces - Altera cyclone V Technical Reference

17-12

EMAC Internal Interfaces

EMAC Internal Interfaces
DMA Master Interface
The DMA interface acts as a bus master on the system interconnect. Two types of data are transferred on
the interface: data descriptors and actual data packets. The interface is very efficient in transferring full
duplex Ethernet packet traffic. Read and write data transfers from different DMA channels can be
performed simultaneously on this port, except for transmit descriptor reads and write-backs, which
cannot happen simultaneously.
DMA transfers are split into a software configurable number of burst transactions on the interface. The
AXI_Bus_Mode
The interface assigns a unique ID for each DMA channel and also for each read DMA or write DMA
request in a channel. Data transfers with distinct IDs can be reordered and interleaved.
The DMA interface can be configured to perform cacheable accesses. This configuration can be done in
the System Manager when the DMA interface is inactive.
Write data transfers are generally performed as posted writes with OK responses returned as soon as the
system interconnect has accepted the last beat of a data burst. Descriptors (status or timestamp), however,
are always transferred as non-posted writes in order to prevent race conditions with the transfer complete
interrupt logic.
The slave may issue an error response. When that happens, the EMAC disables the DMA channel that
generated the original request and asserts an interrupt signal. The host must reset the EMAC with a hard
or soft reset to restart the DMA to recover from this condition.
The EMAC supports up to 16 outstanding transactions on the interface. Buffering outstanding transac‐
tions smooths out back pressure behavior improving throughput when resource contention bottlenecks
arise under high system load conditions.
Related Information
• DMA Controller
Information regarding DMA Controller functionality
• System Manager
Timestamp Interface
The timestamp clock reference can come from either the Clock Manager or the FPGA fabric. If the FPGA
has implemented the serial capturing of the timestamp interface, then the FPGA must provide the PTP
clock reference.
In addition to providing a timestamp clock reference, the FPGA can monitor the pulse-per-second output
from each EMAC module and trigger a snapshot from each auxiliary time stamp timer.
The following table lists the EMAC to FPGA IEEE1588 Timestamp Interface signals to and from each
EMAC module.
Altera Corporation
register in the group is used to configure bursting behavior.
dmagrp
on page 17-16
on page 5-1
2016.10.28
Ethernet Media Access Controller
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