Altera cyclone V Technical Reference page 280

Hard processor system
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5-86
nand
nand Fields
Bit
12
rdfifoderr
11
rdfifoserr
10
wrfifoderr
9
wrfifoserr
8
eccbufderr
7
eccbufserr
6
rdfifoinjd
5
rdfifoinjs
Altera Corporation
Name
This bit is an interrupt status bit for NAND RDFIFO
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in NAND RDFIFO RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for NAND RDFIFO
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
NAND RDFIFO RAM. Software needs to write 1 into
this bit to clear the interrupt status.
This bit is an interrupt status bit for NAND WRFIFO
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in NAND WRFIFO RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for NAND WRFIFO
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
NAND WRFIFO RAM. Software needs to write 1 into
this bit to clear the interrupt status.
This bit is an interrupt status bit for NAND
ECCBUFFER RAM ECC double bit, non-correctable
error. It is set by hardware when double bit, non-
correctable error occurs in NAND ECCBUFFER
RAM. Software needs to write 1 into this bit to clear
the interrupt status.
This bit is an interrupt status bit for NAND
ECCBUFFER RAM ECC single, correctable error. It is
set by hardware when single, correctable error occurs
in NAND ECCBUFFER RAM. Software needs to
write 1 into this bit to clear the interrupt status.
Changing this bit from zero to one injects a double,
non-correctable error into the NAND RDFIFO RAM.
This only injects one double bit error into the NAND
RDFIFO RAM.
Changing this bit from zero to one injects a single,
correctable error into the NAND RDFIFO RAM. This
only injects one error into the NAND RDFIFO RAM.
Description
cv_5v4
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
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