Altera cyclone V Technical Reference page 369

cv_5v4
2016.10.28
Module Instance
sysmgr
Offset:
0x5D4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GPLMUX0 Fields
Bit
0
sel
GPLMUX1
Selection between GPIO and LoanIO output and output enable for GPIO1 and LoanIO1. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x5D8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Manager
Send Feedback
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select source for GPIO/LoanIO 0. 0 : LoanIO 0
controls GPIO/LOANIO[0] output and output enable
signals. 1 : GPIO 0 controls GPIO/LOANI[0] output
and output enable signals.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
GPLMUX1
Register Address
0xFFD085D4
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD085D8
5-175
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
Altera Corporation