Altera cyclone V Technical Reference page 489

Hard processor system
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cv_5v4
2016.10.28
31
30
15
14
Reserved
l4mp Fields
Bit
9
gpio2
8
gpio1
7
gpio0
System Interconnect
Send Feedback
29
28
27
26
13
12
11
10
Name
Controls whether secure or non-secure masters can
access the GPIO 2 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the GPIO 1 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the GPIO 0 slave.
Value
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
gpio2
gpio1
gpio0
acpid
map
WO
WO
WO
0x0
0x0
0x0
WO
0x0
Description
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
21
20
19
18
5
4
3
2
emac1
emac0
sdmmc
qspir
egs
WO
WO
WO
0x0
0x0
0x0
WO
0x0
Access
7-41
l4mp
17
16
1
0
dap
fpgamgr-
regs
WO
0x0
WO 0x0
Reset
WO
0x0
WO
0x0
WO
0x0
Altera Corporation

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