Altera cyclone V Technical Reference page 861

13-40
Configuration registers Register Descriptions
multiplane_read_enable
Device supports multiplane read command sequence
copyback_disable
Device does not support copyback command sequence
cache_write_enable
Device supports cache write command sequence
cache_read_enable
Device supports cache read command sequence
prefetch_mode
Enables read data prefetching to faster performance
chip_enable_dont_care
Device can work in the chip enable dont care mode
ecc_enable
Enable controller ECC check bit generation and correction
global_int_enable
Global Interrupt enable and Error/Timeout disable.
twhr2_and_we_2_re
tcwaw_and_addr_2_data
re_2_we
on page 13-56
Timing parameter between re high to we low (Trhw)
acc_clks on page 13-57
Timing parameter from read enable going low to capture read data
number_of_planes
Number of planes in the device
pages_per_block
Number of pages in a block
device_width
I/O width of attached devices
device_main_area_size
Page main area size of device in bytes
device_spare_area_size
Page spare area size of device in bytes
two_row_addr_cycles
Attached device has only 2 ROW address cycles
multiplane_addr_restrict
Address restriction for multiplane commands
ecc_correction
Correction capability required
read_mode
The type of read sequence that the controller will follow for pipe read commands.
Altera Corporation
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cv_5v4
2016.10.28
NAND Flash Controller
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