Features Of The Hps-Fpga Bridges - Altera cyclone V Technical Reference

2016.10.28
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This chapter describes the bridges in the hard processor system (HPS) used to communicate data between
the FPGA fabric and HPS logic. The bridges use the Advanced Microcontroller Bus Architecture (AMBA)
Advanced eXtensible Interface (AXI) protocol, and are based on the AMBA Network Interconnect
(NIC-301).
The HPS contains the following HPS-FPGA bridges:
• FPGA-to-HPS Bridge
• HPS-to-FPGA Bridge
• Lightweight HPS-to-FPGA Bridge
Related Information
Functional Description of the FPGA-to-HPS Bridge
•
HPS-to-FPGA Bridge Clocks and Resets
•
• Lightweight HPS-to-FPGA Bridge Clocks and Resets
• http://infocenter.arm.com
Additional information is available in the AMBA AXI Protocol Specification v1.0 and the AMBA
Network Interconnect (NIC-301) Technical Reference Manual, which you can download from the
ARM Infocenter website.

Features of the HPS-FPGA Bridges

The HPS-FPGA bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic
and vice versa. For example, if you implement memories or peripherals in the FPGA fabric, HPS
components such as the MPU can access them. Components implemented in the FPGA fabric, such as the
Nios II processor, can also access memories and peripherals in the HPS logic.
®
Table 8-1: HPS-FPGA Bridge Features
Supports the AMBA AXI3 interface protocol
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Feature
HPS-FPGA Bridges
on page 8-4
on page 8-52
on page 8-52
FPGA-to-HPS HPS-to-FPGA
Bridge Bridge
Y
Lightweight HPS-to-
FPGA Bridge
Y Y
8
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