Altera cyclone V Technical Reference page 83

2-46
l4src
tracediv Fields
Bit
2:0
traceclk
l4src
Contains fields that select the clock source for L4 MP and SP APB interconnect Fields are only reset by a
cold reset.
Module Instance
clkmgr
Offset:
0x70
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
The dbg_trace_clk is divided down from the C2
output of the Main PLL by the value specified in this
field.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Value
Divide By 1
Divide By 2
Divide By 4
Divide By 8
Divide By 16
Reserved
Reserved
Reserved
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Register Address
0xFFD04070
21 20 19
5 4 3
cv_5v4
2016.10.28
Access Reset
RW 0x0
18 17 16
2 1 0
l4sp l4mp
RW RW 0x0
0x0
Clock Manager
Send Feedback