Altera cyclone V Technical Reference page 460

7-12
Bit Fields for Modifying the Memory Map
Note: L2 filter registers in the MPU subsystem, not the interconnect, allow the SDRAM to be remapped to
address
Related Information
• L3 (NIC-301) GPV Registers Address Map
Information about the GPV registers
• remap
Description of the
The SDRAM Region
•
Information about L2 cache filtering, including the address filter start and address filter end registers
Cortex-A9 Microprocessor Unit Subsystem
•
For general information about the MPU subsystem, refer to the Cortex-A9 Microprocessor Unit
Subsystem chapter.
HPS Peripheral Master Input IDs
•
For information about virtual ID mapping in the ACP ID mapper, refer to "HPS Peripheral Master
Input IDs" in the Cortex-A9 Microprocessor Unit Subsystem chapter.
Bit Fields for Modifying the Memory Map
Table 7-3: remap Bit Fields
Bit Name
mpuzero
nonmpuzero
Reserved
Altera Corporation
for the MPU.
0x0
on page 7-32
register
remap
on page 9-11
Bit Offset
0
Value Meaning
0
1
This bit has no effect on non-MPU masters.
Note: Regardless of this setting, the boot ROM also always maps to
1
Value Meaning
0
1
This bit has no effect on the MPU L3 master.
Note that regardless of this setting, the on-chip RAM also always maps
to address 0xFFFD0000 for the non-MPU L3 masters.
2 Must always be 0.
on page 7-23
on page 9-1
on page 9-34
The boot ROM maps to address 0x0 for the MPU L3 master
The on-chip RAM maps to address 0x0 for the MPU L3 master
address 0xFFFF0000 and the on-chip RAM also always
maps to address 0xFFFD0000 for the MPU L3 master.
The SDRAM maps to address 0x0 for the non-MPU L3 masters
The on-chip RAM maps to address 0x0 for the non-MPU
masters
Description
cv_5v4
2016.10.28
System Interconnect
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