Altera cyclone V Technical Reference page 132

cv_5v4
2016.10.28
Bit
21
etrstallreq
20
etrstallen
18
fpgahsack
17
fpgahsreq
16
fpgahsen
14
scanmgrhsack
13
scanmgrhsreq
Reset Manager
Send Feedback
Name
Software writes this field 1 to request to the ETR that
it stalls its AXI master to the L3 Interconnect.
Software waits for the ETRSTALLACK to be 1 and
then writes this field to 0. Note that it is possible for
the ETR to never assert ETRSTALLACK so software
should timeout if ETRSTALLACK is never asserted.
This field controls whether the ETR is requested to
idle its AXI master interface (i.e. finish outstanding
transactions and not initiate any more) to the L3
Interconnect before a warm or debug reset. If set to 1,
the Reset Manager makes a request to the ETR to stall
its AXI master and waits for it to finish any
outstanding AXI transactions before a warm reset of
the L3 Interconnect or a debug reset of the ETR. This
stalling is required because the debug logic (including
the ETR) is reset on a debug reset and the ETR AXI
master is connected to the L3 Interconnect which is
reset on a warm reset and these resets can happen
independently.
This is the acknowlege (high active) that the FPGA
handshake acknowledge has been received by Reset
Manager.
Software writes this field 1 to initiate handshake
request to FPGA . Software waits for the
FPGAHSACK to be active and then writes this field to
0. Note that it is possible for the FPGA to never assert
FPGAHSACK so software should timeout in this case.
This field controls whether to perform handshake
with FPGA before asserting warm reset. If set to 1, the
Reset Manager makes a request to the FPGAbefore
asserting warm reset signals. However if FPGA is
already in warm reset state, the handshake is not
performed. If set to 0, the handshake is not performed
This is the acknowlege (high active) that the SCAN
manager has successfully idled its output clocks.
Software writes this field 1 to request to the SCAN
manager to idle its output clocks. Software waits for
the SCANMGRHSACK to be 1 and then writes this
field to 0. Note that it is possible for the Scan Manager
to never assert SCANMGRHSACK (e.g. its input
clock is disabled) so software should timeout in this
case.
Description
3-21
ctrl
Access Reset
RW 0x0
RW 0x1
RO 0x0
RW 0x0
RW 0x0
RO 0x0
RW 0x0
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