Fpga Emac I/O Signals - Altera cyclone V Technical Reference

17-8

FPGA EMAC I/O Signals

phy_rxdv_i
Note: The "n" in EMACn stands for the EMAC peripheral number.
Related Information
EMAC HPS Interface Initialization
Information on how to initialize RGMII interface
FPGA EMAC I/O Signals
Table 17-2: FPGA EMAC I/O Signals
emac_clk_tx_i
emac_phy_txclk_o
Altera Corporation
EMAC Port
PHY Receive Data
Valid
on page 17-66
Signal Name
Transmit Clock
Transmit Clock
Output
In/Out Width
This signal is driven by the PHY
In 1
and functions as the receive
control signal used to qualify the
data received on
signal is sampled on both edges
of the clock. Note that the signal
phy_rxdv_i
RX_CTL
In/Out Width
In 1 This is the transmit clock (2.5
MHz/25 MHz) provided by the
MII PHYs only. This clock comes
from the FPGA Interface and is
used for TX data capture. This
clock is not used in GMII mode.
Note: This clock must be
Out 1 In GMII mode, this signal is the
transmit clock output to the PHY
to sample data.
For MII, this clock is unused.
Description
. This
phy_rxd_i
is assigned to pin
in the device pin-out.
Description
able to perform glitch
free switching
between 2.5 and 25
MHz.
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cv_5v4
2016.10.28